Last week, several members of InfoSec Global team, including myself, attended Synopsys’ ARC Processor Summit on embedded systems and their applications. The main theme of this summit was how to use ARC processors to improve efficiency and performance in a variety of situations. Another topic that several presenters touched on was cyber security. Both themes tied in nicely with one of InfoSec Global’s main goals: to make hardware accelerators the core of security, which is cryptography.
There were three parallel tracks at this 2022 summit:
2. Artificial Intelligence (AI)
3. Enabling Technologies
As part of the third track, Ruud Derwig from Synopsys and I did a joint presentation on Post-Quantum Cryptography: Theory to Accelerated Practice. After sharing a crash course on PQC, they covered recent developments including the National Security Agency’s (NSA) recommendations to migrate to their Commercial National Security Algorithm Suite 2.0 (CNSA 2.0). They also shared the work being done on a joint project between Synopsys and InfoSec Global to take PQC to the next level by building specialized hardware.
There was high interest in the topic, with many attendees asking informed and engaging questions. Conference participants were well-aware of NIST’s new PQC standards, which will inevitably be followed by a full mandate for cryptographic migration to PQC. Due to the lengthy design-time and lifecycle of hardware, designing specialized processors for PQC is a relevant and exciting proposal.
The presentation covered how the hardware accelerated cryptography can be built and can be used. Some parts of the new PQC algorithms utilize cryptographic algorithms that already have hardware acceleration, for example certain hash functions, while other parts of these algorithms must be built from scratch.
As NIST has only recently revealed certain new PQC algorithms for standardization, with additional standards on the way, it is unfortunately necessary to design processors with the understanding that they will likely need to run cryptographic algorithms that have not yet been chosen. Therefore, the overall design must be crypto-agile. For this reason, the presentation also covered which hardware components can be reused by multiple algorithms.
In parallel to the above presentation, InfoSec Global Head of System Engineering, Eng Kiat Low, presented a demo of crypto agility at the trust authority level via PQC.
Overall, this well-attended summit covered many interesting topics, as the industry looks at the applicability of ARC to a variety of real-world problems, including how to build hardware accelerated PQC.